This invention relates to the production method for a semiconductor device, particularly to the element isolation technique utilizing an insulating material and a semiconductor device which is manufactured by means of this technique. As isolation technique in semiconductor integrated circuits, there are generally known methods in which the isolation regions are formed by selective oxidation for facilitating higher packaging density and a more effective manufacturing process. According to such methods, since the periphery of the active region is surrounded by the oxide layer, self-alignment is possible by methods such as base diffusion so that unnecessary parts which have been conventionally required for masking may be eliminated. This allows a higher packaging density. Furthermore, since on the sides of element region are disposed deep oxide layers, the coupling capacitance is significantly reduced. This method, however, adopts a structure in which the thermally oxidized layer is selectively embedded in the silicon substrate. This causes a great strain in the silicon substrate, degrades the electrical characteristics of the element, and thus imposes strict limits as to the selection of the structure, configuration, film thickness, the conditions for selective oxidation of the oxidation mask, and occasionally on the selection of the material itself for the silicon substrate. This is disclosed, for example, in IEDM, "High Pressure Oxidation for Isolation of High Speed Bipolar Devices", pp. 340-343, 1979.
In the conventional element isolation technique utilizing an insulating material, the field oxidizing time is long. This gives a significant rise to the diffusion and redistribution of the impurity layer in the channel stopper. For example, when the diffusion in the transverse direction is great, the effective channel width of the MOS transistor is reduced and the drain coupling capacitance increases, thus obstructing realization of a high speed device.
Also, if thermal oxidation is effected using a silicon nitride layer as mask, a silicon nitride layer called "white ribbon" is formed in the silicon substrate below the silicon nitride layer, causing a poor voltage resistivity in the element. Moreover, as a double-layer mask composed of a silicon nitride layer and an oxide layer is used as an oxidation-proof mask, a bird's beak of almost 1 .mu.m is thrusted into below the silicon nitride layer. As a result, it was difficult to form an isolation layer with the distance between elements been less than 2 .mu.m. This is reported, for instance, in "Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selection Oxidation", pp. 216-222, J.E.C.S., 1980.